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| author | Karl Hallsby <karl@hallsby.com> | 2023-10-03 00:39:55 -0500 |
|---|---|---|
| committer | Karl Hallsby <karl@hallsby.com> | 2023-10-03 00:39:55 -0500 |
| commit | af791397a75540419a9ce050d0f779b3cea13695 (patch) | |
| tree | e45778b803cf4f15d058b55bbe87a21be1d759e2 | |
| parent | 1b2cdf461bfcd51a0e8a9ad02721e2527234db8b (diff) | |
Add Verilator & GTKWave debugging to Village project
| -rw-r--r-- | Research.tex | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Research.tex b/Research.tex index b0c959f..da4a0d1 100644 --- a/Research.tex +++ b/Research.tex @@ -7,6 +7,7 @@ \item Identified \href{https://riscv.org}{RISC-V} \href{https://github.com/riscv/riscv-v-spec/releases/tag/v1.0}{V-extension} as good candidate for VCODE acceleration \item Designed VCODE accelerator as RoCC coprocessor in \href{https://chisel-lang.org}{Chisel} and integrated with \href{https://chipyard.readthedocs.io/en/stable}{Chipyard} \item Implemented both unit tests and baremetal full-program tests for coprocessor +\item Debugged design using Verilator, a cycle-accurate behavioral simulator and GTKWave, a waveform viewer \end{notopsepitemize} \subsection{Virtine Accelerator}, \Location{\IIT{}, Chicago, IL} \hfill \Daterange{2021}{06}{01}{2021}{08}{31}\\ |