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| author | Karl Hallsby <karl@hallsby.com> | 2022-08-08 16:14:57 -0500 |
|---|---|---|
| committer | Karl Hallsby <karl@hallsby.com> | 2022-08-08 16:44:46 -0500 |
| commit | 56a046f2e20e0c63b33fdaa54564f49cce2dc684 (patch) | |
| tree | c6d415603a970d3862708615b9cab4b126358441 | |
| parent | a2964e510e673e6cd258ab58150310173c75db9f (diff) | |
Add summer 2022 Northwestern REU experience
| -rw-r--r-- | _pages/experience.markdown | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/_pages/experience.markdown b/_pages/experience.markdown index d1778f3..ffec064 100644 --- a/_pages/experience.markdown +++ b/_pages/experience.markdown @@ -5,6 +5,15 @@ permalink: /experience/ description: Listing of all my professional experiences. nav: true --- +# [Northwestern University](https://northwestern.edu) +Evanston, IL<br> +Summer 2022 + + * Helped implement back-end [VCODE](https://dl.acm.org/doi/boom/10.5555/865063) code generation for an LLVM-based compiler. + * Identified [RISC-V](https://riscv.org) [V-extension](https://github.com/riscv/riscv-v-spec/releases/tag/v1.0) as good candidate for VCODE acceleration. + * Designed VCODE accelerator as RoCC coprocessor in [Chisel](https://www.chisel-lang.org) and integrated with [Chipyard](https://chipyard.readthedocs.io/en/stable). + * Implemented both unit tests and baremetal full-program tests for coprocessor. + # [Illinois Institute of Technology](https://www.iit.edu) Chicago, IL<br> Summer 2021 |