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authorKarl Hallsby <karl@hallsby.com>2022-08-08 17:02:20 -0500
committerKarl Hallsby <karl@hallsby.com>2022-08-08 17:02:20 -0500
commit51d8c1e4c6bdf6d061914d6a4fdde899372ef572 (patch)
tree906ae8d40535c23dbc157afee44c0918181fd269
parentfba744974d403278aea35d753b6021646419f951 (diff)
Correct VCODE link
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1 files changed, 1 insertions, 1 deletions
diff --git a/_pages/experience.markdown b/_pages/experience.markdown
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@@ -9,7 +9,7 @@ nav: true
Evanston, IL<br>
Summer 2022
- * Helped implement back-end [VCODE](https://dl.acm.org/doi/boom/10.5555/865063) code generation for an LLVM-based compiler.
+ * Helped implement back-end [VCODE](https://dl.acm.org/doi/10.5555/865063) code generation for an LLVM-based compiler.
* Identified [RISC-V](https://riscv.org) [V-extension](https://github.com/riscv/riscv-v-spec/releases/tag/v1.0) as good candidate for VCODE acceleration.
* Designed VCODE accelerator as RoCC coprocessor in [Chisel](https://www.chisel-lang.org) and integrated with [Chipyard](https://chipyard.readthedocs.io/en/stable).
* Implemented both unit tests and baremetal full-program tests for coprocessor.