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+layout: article
+title: "Chipyard, RISC-V, and Chisel"
+date: 2021-06-10
+categories: riscv
+tags: RISC-V Chipyard Chisel FPGA
+---
+For the past semester (Spring 2021), [Alex Lukens](https://alukens.com){:target="_blank"} and I have been researching [Chipyard](https://github.com/ucb-bar/chipyard){:target="_blank"}, a CPU design environment.
+This tool is designed to bring Agile and CI/CD development practices to the hardware design world.
+In particular, Chipyard is intended to provide parameterized **declaration** of [RISC-V](https://riscv.org){:target="_blank"} CPU designs.
+Chipyard is based on the [Chisel](https://www.chisel-lang.org/){:target="_blank"} domain-specific language.
+Together, we investigated Chipyard and RISC-V, attempting to determine if such an environment benefits the RISC-V community and its potential uses.
+Our findings are collected as a introductory-style manual, presented at the end of this [post](#report).
+
+# RISC-V #
+To start with, RISC-V is the fifth revision of a [RISC](https://en.wikipedia.org/wiki/Reduced_instruction_set_computer){:target="_blank"} [ISA (Instruction Set Architecture)](https://en.wikipedia.org/wiki/Instruction_set_architecture){:target="_blank"} **specification** from the University of California, Berkeley.
+Some other processors that use RISC designs include: Atmel AVR (used by Arduinos), ARM (used in nearly all mobile devices, including Apple's new [Apple Silicon](https://www.macrumors.com/guide/apple-silicon/){:target="_blank"}), PowerPC (previously used by Apple), SPARC, and several others.
+In short, a RISC processor is one where the processor will only access memory to fetch the next instruction, leading to one instruction being executed every CPU cycle.
+This is in contrast to [CISC](https://en.wikipedia.org/wiki/Complex_instruction_set_computer) processors, which typically use _many_ memory accesses to complete an operation.
+Due to instructions usually taking just one clock cycle on a RISC design, and instructions usually having constant length, allows for many optimizations that can improve performance and/or power consumption.
+
+[RISC-V](https://riscv.org){:target="_blank"} is a somewhat vague term.
+RISC-V is technically a processor specification with many optional components, allowing for processors to be tailored to particular uses.
+A RISC-V processor is used to describe a processor that **implements** the RISC-V ISA.
+There is also the RISC-V organization which works to further refine and develop the RISC-V ISA standard, ecosystem, and associated resources.
+Chipyard is an environment to develop accelerators and processors that meet the RISC-V ISA standard.
+
+# Chisel #
+[Chisel](https://www.chisel-lang.org/) is a [declarative](https://en.wikipedia.org/wiki/Declarative_programming) [DSL (Domain Specific Language)](https://en.wikipedia.org/wiki/Domain-specific_language) written and embedded inside [Scala](https://www.scala-lang.org/).
+This allows us to parameterize and generate Verilog modules that fulfill the requested purpose without having to handle [HDLs (Hardware Description Languages)](https://en.wikipedia.org/wiki/Hardware_description_language), like [Verilog](https://en.wikipedia.org/wiki/Verilog).
+Because Chisel uses Scala, which depends on the JVM, Chisel can be used on any platform that supports the JVM and associated tools.
+In addition, because Scala's strict typechecking is used to validate **generated** designs before being elaborated to Verilog.
+Chisel forms the backbone of Chipyard, and many other RISC-V components.
+
+# Chipyard #
+[Chipyard](https://github.com/ucb-bar/chipyard) is a [RISC-V](https://riscv.org) development environment, built using [Chisel](https://www.chisel-lang.org/).
+Because both Chipyard and its dependencies are built using Chisel, the chip designer can **declaratively** define an accelerator or processor design.
+In addition, it is designed in such a way that custom circuit HDL and associated Chisel code can be added be added to the ecosystem.
+This allows for arbitrary extension of Chipyard to meet any particular demand.
+
+# Report #
+This report covers how to set up Chipyard to design and simulate designs, and write them out to an [FPGA](https://en.wikipedia.org/wiki/Field-programmable_gate_array).
+It goes into an in-depth discussion of Chipyard's structure and how to work with it.
+Later sections explore potential uses of RISC-V and Chipyard at [Illinois Institute of Technology](https://www.iit.edu/) ([Alex's](https://alukens.com) and my university).
+
+{% pdf "/assets/chipyard-intro.pdf" %}
+You must have a PDF viewer for the file to be displayed as a part of this page.
+Otherwise, you must download and open the file manually.