\section{Research}\label{sec:Research}
\subsection{\PLab{}}\hfill\DatetoPresent{2023}{09}{01}\\
\emph{Research Assistant}, \Advisor{\PDinda{} \& \NHardav{}}\hfill\Daterange{2022}{06}{00}{2022}{09}{00}
\begin{notopsepitemize}
\item Systems research into unifying software and hardware for performant parallelism
\item Investigate usage of software time-travel debugging techniques to improve hardware design workflows
\item Modify RISC-V designs to enable faster trap dispatching without changing privilege levels
\item Implement accelerators on RISC-V for high-level data-parallel languages in \href{https://chisel-lang.org}{Chisel} and \href{https://chipyard.readthedocs.io/en/stable}{Chipyard}
\item Use deep understanding of RISC-V ISA to collaborate with other labs, helping facilitate their research
\end{notopsepitemize}

\subsection{\HExSA{}}\hfill\Daterange{2021}{06}{00}{2021}{08}{00}\\
\emph{Undergraduate Researcher}, \Advisor{\KHale{}}
\begin{notopsepitemize}
\item Created FPGA design to accelerate virtual machine clean-up, branching off of work another Ph.~D student completed
\item Developed \textsc{Linux} PCIe kernel module to initialize and communicate with flashed hardware design
\item Exposed FPGA capabilities as character device for programmer interaction
\item Wrote \href{https://www.qemu.org/}{QEMU} device to emulate physical device's behavior and validate kernel module functionality
\end{notopsepitemize}

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