From 1283b1aafcf597ed6b48c14f3f8d0fe28950039b Mon Sep 17 00:00:00 2001
From: Karl Hallsby <karl@hallsby.com>
Date: Sat, 26 Oct 2024 16:19:05 -0500
Subject: Update Research section to be more encompassing of my roles

Hopefully, this will also make my work less "scoopable" too, but that
is not a major concern of mine.
---
 Research.tex | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

(limited to 'Research.tex')

diff --git a/Research.tex b/Research.tex
index f083d81..49b82c0 100644
--- a/Research.tex
+++ b/Research.tex
@@ -1,18 +1,16 @@
 \section{Research}\label{sec:Research}
-\subsection{Village Project}, \Location{\NU{}, Evanston, IL} \hfill \DatetoPresent{2022}{06}{01}\\
-\Advisor{\PDinda{}}\\
-\emph{Research Assistant --- \href{http://presciencelab.org/}{Prescience Lab}} \hfill {~}
+\subsection{\PLab{}}\hfill\DatetoPresent{2023}{09}{01}\\
+\emph{Research Assistant}, \Advisor{\PDinda{} \& \NHardav{}}\hfill\Daterange{2022}{06}{00}{2022}{09}{00}
 \begin{notopsepitemize}
-\item Helped implement back-end \href{https://dl.acm.org/doi/10.5555/865063}{VCODE} code generation for an LLVM-based compiler
-\item Identified \href{https://riscv.org}{RISC-V} \href{https://github.com/riscv/riscv-v-spec/releases/tag/v1.0}{V-extension} as good candidate for VCODE acceleration
-\item Designed VCODE accelerator as RoCC coprocessor in \href{https://chisel-lang.org}{Chisel} and integrated with \href{https://chipyard.readthedocs.io/en/stable}{Chipyard}
-\item Implemented both unit tests and baremetal full-program tests for coprocessor
-\item Debugged design using Verilator, a cycle-accurate behavioral simulator and GTKWave, a waveform viewer
+\item Systems research into unifying software and hardware for performant parallelism
+\item Investigate usage of software time-travel debugging techniques to improve hardware design workflows
+\item Modify RISC-V designs to enable faster trap dispatching without changing privilege levels
+\item Implement accelerators on RISC-V for high-level data-parallel languages in \href{https://chisel-lang.org}{Chisel} and \href{https://chipyard.readthedocs.io/en/stable}{Chipyard}
+\item Use deep understanding of RISC-V ISA to collaborate with other labs, helping facilitate their research
 \end{notopsepitemize}
 
-\subsection{Virtine Accelerator}, \Location{\IIT{}, Chicago, IL} \hfill \Daterange{2021}{06}{01}{2021}{08}{31}\\
-\Advisor{\KHale{}}\\
-\emph{\href{http://datasys.cs.iit.edu/grants/BigDataX/2021/index.html}{Student Researcher} --- \href{http://mystic.cs.iit.edu/}{Mystic}} \hfill {~}
+\subsection{\HExSA{}}\hfill\Daterange{2021}{06}{00}{2021}{08}{00}\\
+\emph{Undergraduate Researcher}, \Advisor{\KHale{}}
 \begin{notopsepitemize}
 \item Created FPGA design to accelerate virtual machine clean-up, branching off of work another Ph.~D student completed
 \item Developed \textsc{Linux} PCIe kernel module to initialize and communicate with flashed hardware design
-- 
cgit v1.2.3

