From 5deefa0ff2bcfdde256196ee03cd9072980fbfad Mon Sep 17 00:00:00 2001
From: Karl Hallsby <karl@hallsby.com>
Date: Mon, 8 Aug 2022 19:35:57 -0500
Subject: Add Chisel HDL proficiency

---
 Skills.tex | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Skills.tex b/Skills.tex
index 47bcf11..fe4ac5c 100644
--- a/Skills.tex
+++ b/Skills.tex
@@ -15,6 +15,7 @@
 \begin{itemize}[noitemsep]
 \item Verilog
 \item VHDL
+\item \href{https://chisel-lang.org}{Chisel}
 \end{itemize}
 
 \columnbreak{}
-- 
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